As one aspect of electronic devices, a three-dimensional stacked device in which substrates, such as a semiconductor chip and a semiconductor wafer, are stacked is known.
As a method for manufacturing the three-dimensional stacked device, there is a method including forming a hole penetrating one substrate of upper and lower substrates bonded to each other through a resin layer and the resin layer using a through silicon via (TSV) technique, and then forming a conductor via, the side surface of which is covered with a barrier film, in the hole.
In the manufacturing of the three-dimensional stacked device, a process including heating is carried out. After the process including heating, a residual stress may be generated around the conductor via in the resin layer due to thermal expansion coefficient differences among the materials of the substrates, the conductor via, and the resin layer. The residual stress has a possibility of causing peeling between the materials. As a technique of avoiding the generation of the residual stress, a technique of providing a post (insulating film and the like) having a predetermined thermal expansion coefficient in such a manner as to surround the conductor via in the resin layer has been proposed.
However, also in the three-dimensional stacked device disposed with the above-described post, when the number of times of heating processes in the manufacturing thereof and the like increases, so that the expansion and the contraction of the contained materials are repeated, there is a possibility that a gap may be formed in a region between the resin layer and the conductor via in the resin layer due to the thermal expansion coefficient differences among the materials. Such a gap may cause a reduction in the barrier property of the barrier film covering the side surface of the conductor via and a reduction in the characteristics and the reliability of the three-dimensional stacked device due to the reduction in the barrier property.
The following is a reference document:    [Document 1] Japanese Laid-open Patent Publication No. 2010-226060.